This invention relates generally to testing systems for evaluation of circuit logic, and more particularly to providing a system that provides automatic building and testing of component updates in a software and hardware model.
Testing of prototype hardware and/or software is routinely performed. Efficient techniques for performing testing involve environments providing simulation. In the past, model build processes have experienced various build problems. For example, no formal method exists for expressing inter-component dependencies; failures in less critical components were slowing the adoption of critical components; components had no way of independently testing there quality at the model level before releasing; simple repetitive tasks were being done by engineers; inconsistent delivery of components from varied groups.
One example is provided in U.S. Pat. No. 6,490,545, entitled “Method and apparatus for adaptive co-verification of software and hardware designs.” In this patent, a simulation system is provided for simulating behavior of a device for implementing an algorithm using a software model and a hardware model which are converted to a common programming language and mathematical notation. The simulation system uses the same input user interface for the software model and the hardware model. The simulation system uses the same output user interface for generating the simulation results for both the software model and the hardware model in the common programming language and mathematical notation, purportedly allowing a user to verify and analyze the software and hardware simulation results for optimization of the device. Unfortunately, this system calls for considerable interfacing, and is therefore not very efficient from the perspective of a user.
Another example of simulation is provided in U.S. Pat. No. 6,353,806, entitled “System level hardware simulator and its automation.” This patent discloses an apparatus that provides for automatically generating symbolic models and developing a system level hardware simulator. The system to be simulated is subdivided into a plurality of system layers which are associated with symbolic model symbols. The specification of a symbolic model symbol represents a functionality of a system layer, a subset of the system hierarchy. Each symbolic model symbol reads from its allocated memory, gathers input from associated symbolic model symbols, updates its register contents and broadcasts updates to associated symbolic model symbols, as per its specification, completing a cycle of simulation when a complete chain of associated symbolic model symbols is updated. A displayed symbolic model can be interacted with to modify the model by altering the interconnections of the displayed symbolic model causing corresponding modification of the connections of other interconnected symbolic model symbols and their associated input/output memories. The simulator operates as a real time event simulator through further linkage of symbolic model symbols to timing information specifying real-time propagation and time delays. Unfortunately, this patent only describes a hardware simulator, and does not accommodate a combined hardware and software simulation environment.
Thus, what are needed are techniques for testing hardware and software, where the techniques overcome problems cited in the prior art. Preferably, the process will reduce the number of errors found in hardware model builds and release and make finding problem in the model build easier and quicker.